The present invention relates to a single supply voltage, nonvolatile memory device with cascoded column selection and simultaneous word read/write operations.
In particular, the present invention advantageously, but not exclusively, finds application in nonvolatile phase change memory devices, to which the following discussion will make explicit reference without any loss of generality thereby.
As is known, nonvolatile memory devices comprise a memory array formed by memory cells arranged in rows and columns, wherein word lines connect the gate terminals of the cells arranged on a same row and bit lines connect the array access device terminals (commonly drain terminals) of the cells arranged on one and the same column.
Individual rows of the memory array are addressed by a row decoder which receives an encoded address and biases the word line of the row being addressed at a stable and precise voltage, the value whereof depends upon the operation to be performed (read, program, verify, erase), while individual columns of the memory array are selected by a column selector which receives the outputs of a column decoder supplied with the above encoded address. The bitline of the column being addressed is biased such as to ensure that the array access device terminal of the memory cell addressed is biased at a preset electrical potential, which depends on the operation to be performed; this potential must be precise, stable and controlled since its precision affects not only the precision of the levels programmed in the memory cells, but also the programming time of the memory cells or, in read operation, the correct detection of the cell""s content.
Phase change memory (PCM) devices are based on storage elements that use a class of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous, disorderly phase to a crystalline or polycrystalline, orderly phase, and the two phases are associated to considerably different values of resistivity.
At present, alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase-change cells. The chalcogenide that currently offers the most promise is formed by a Ge, Sb and Te alloy (Ge2Sb2Te5) and is widely used for storing data in overwritable disks.
In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the crystalline phase (more conductive) and vice versa. The characteristics of the chalcogenides in the two phases are shown in FIG. 1. As may be noted, at a given read voltage, here designated by Vr, there is a variation in resistance of more than 10.
Phase change may be obtained by locally increasing the temperature, as shown in FIG. 2. Below 150xc2x0 C. both phases are stable. Above 200xc2x0 C. (nucleation starting temperature, designated by Tx), there takes place fast nucleation of the crystallites, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t2), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature Tm (approximately 600xc2x0 C.) and then to cool the chalcogenide off rapidly (time t1).
From the electrical standpoint, it is possible to reach both the critical temperatures, namely the crystallization temperature and the melting point, by causing a current to flow through a resistive element which heats the chalcogenic material by the Joule effect.
The basic structure of a phase change storage element 1 which operates according to the principles described above is shown in FIG. 3 and comprises a resistive element 2 (heater) and a programmable element 3. The programmable element 3 is made with a chalcogenide and is normally in the crystalline state in order to enable a good flow of current. One part of the programmable element 3 is in direct contact with the resistive element 2 and forms a phase change portion 4.
If an electric current having an appropriate value is made to pass through the resistive element 2, it is possible to heat the phase change portion 4 selectively up to the crystallization temperature or to the melting temperature and to cause phase change.
The state of the chalcogenic material can be measured by applying a sufficiently small voltage, such as not to cause a sensible heating, and by then reading the current that is flowing. Given that the current is proportional to the conductivity of the chalcogenide, it is possible to discriminate wherein state the chalcogenide is.
Of course, the chalcogenide can be electrically switched between different intermediate states, thus affording the possibility of obtaining a multilevel memory.
In practice, a phase change memory element or PCM storage element 1 can be considered as a resistor which conducts a different current according to its phase. In particular, the following convention is adopted: a phase change storage element is defined as xe2x80x9csetxe2x80x9d when, once it is appropriately biased, it conducts a detectable current (this condition may be associated to a logic condition xe2x80x9c1xe2x80x9d) and as xe2x80x9cresetxe2x80x9d when, in the same biasing conditions, it does not conduct current or conducts a much lower current than that of a cell that is set (logic condition xe2x80x9c0xe2x80x9d).
The use of PCM storage elements has already been proposed in memory arrays formed by a plurality of memory cells arranged on rows and columns. In order to prevent the memory cells from being affected by noise caused by adjacent memory cells, generally each memory cell comprises a PCM storage element of the type described above and a selection element, such as a MOS transistor or a diode, in series to the PCM storage element.
When the selection element is a diode, each cell is connected at the intersection of two selection lines, perpendicular to one another, one of which is parallel to the rows of the memory array, while the other is parallel to the columns.
When the selection element is a transistor, different solutions are known which are essentially based upon biasing the source terminal of the selection element at variable voltages that depend upon the reading or programming operation (set, reset) of the memory. For example, according to U.S. Pat. No. 6,314,014, a first terminal of the PCM storage element is biased at a biasing voltage the value of which depends upon the operation (either reading or programming) of the memory cell, a second terminal of the PCM storage element is connected to a drain terminal of the selection transistor, the gate terminal of the selection transistor is connected to a row line, and the source terminal of the selection transistor is connected to a column line. In practice, selection of the memory cell takes place via the source and gate terminals of the selection transistor. Alternatively, the drain terminal of the selection transistor can be biased at the biasing voltage, and the memory cell can be coupled between the source terminal and its own column line.
It is moreover known that nonvolatile memory devices are typically of a single supply voltage type; namely, they receive from outside a single supply voltage currently having a value of 3 Vxc2x110% or else 1.8 Vxc2x110%; hence voltages having much higher values than the supply voltages and required in the various operations performed on the memory cells (read, program, verify, erase) are generated inside the nonvolatile memory device by voltage boosting circuits, generally known as xe2x80x9cvoltage boostersxe2x80x9d or xe2x80x9ccharge pumpsxe2x80x9d.
The boosted voltages supplied by voltage boosting circuits are, however, generally far from stable, and consequently are regulated and stabilized by voltage regulators.
FIG. 4 is a schematic illustration of a known nonvolatile memory device, of which only the parts necessary for understanding the problem to be solved by the present invention are shown.
In particular, in FIG. 4, reference number 10 designates a nonvolatile memory device as a whole, 11 designates the memory array, 12 designates the row decoder, 13 designates the column selector, 14 designates the addressed word line, 15 designates the addressed bit line, 16 designates the addressed phase change memory cell, 17 designates a supply line set at the supply voltage VDD supplied from outside to the nonvolatile memory device 10, 18 designates the charge pump, having an input connected to the supply line 17 and supplying a boosted voltage higher than the supply voltage VDD, and 19 designates the voltage regulator, which receives the boosted voltage and supplies a regulated voltage, which is supplied to the column selector 13 in the programming step.
In particular, for each bit line 15 of the memory array 11, the column selector 13 can be schematically represented by a plurality of selection switches implemented by NMOS or PMOS transistors, connected in series and receiving on their control terminals respective column select signals. The number of selection switches for each bit line 15 depends upon the size of the memory array 11 or of the sectors of the memory array and upon the hierarchical organization of the column selector. FIG. 4 illustrates by way of example a column selector 13 formed, for each bit line 15, by three selection switches, designated by 20, 21 and 22, which receive on their control terminals respective column selection signals YM, YN and YO, which, in turn are generated by a column decoder as well known in the art and that is not indicated here for simplicity.
A selection stage 23, known as xe2x80x9cprogram loadxe2x80x9d is further coupled between the voltage regulator 19 and the column selector 13 and is essentially formed by a controlled switch that connects the column selector 13 to the output of the voltage regulator 19 only during programming for biasing the addressed bit line 15 at a voltage such as to ensure that the array access device terminal (commonly the drain terminal) of the addressed memory cell 16 is supplied with a preset electrical potential, for example in a phase change memory device with MOS architecture of approximately 1 V for setting, 2 V for resetting or 0 V (or floating) if deselected, according to whether the datum that is to be programmed in the memory cell 16 addressed is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
During reading, instead, program load 23 disconnects the charge pump 18 and the voltage regulator 19 from the column selector 13, the latter being thus connected to the output of a read circuit 24, which, as known, carries out reading of the contents of the addressed memory cell 16 by comparing the current flowing in the addressed memory cell 16 (or a quantity correlated thereto) with the current flowing through a reference memory cell (not shown) having known contents.
For a more detailed treatment of a circuit structure of a sense amplifier, see for example European patent application 99830348.1 filed on Apr. 6, 1999 in the name of the present applicant and published as EP-A-1058270.
As described in the above patent application, the read circuit 24 comprises, among others, a biasing stage 25 having a negative feedback cascode structure for biasing the addressed bit line 15 at a voltage such as to ensure that, during reading, a preset electrical potential, typically approximately 0.4 V in a phase change memory device, will be present on the array access device terminal of the addressed memory cell 16.
In particular, the biasing stage 25 comprises an NMOS transistor 26 and a NOR logic gate 27. The NMOS transistor 26 has drain terminal connected to a sense amplifier 28 in turn connected to the supply line 17 set at the supply voltage VDD, which is supplied from outside to the nonvolatile memory device 10, source terminal connected to the column selector 13, and gate terminal connected to the output of the NOR logic gate 27; NOR logic gate 27 has a first input connected to the source terminal of the NMOS transistor 26 and a second input receiving a logic enabling signal EN, that allows the biasing stage 25, and consequently the read circuit 24, to be turned on and off.
In FIG. 4, moreover, A designates the input node of the column selector 13, connected, during reading, to the read circuit 24 and, during programming, to the output of the voltage regulator through the program load 23, B designates the node between the first NMOS transistor 20 and the second NMOS transistor 21 of the column selector 13, C designates the node between the second NMOS transistor 21 and the third NMOS transistor 22 of the column selector 13, and D designates the array access device terminal of the addressed memory cell 16.
From an analysis of the column selection architecture shown in FIG. 4, it may be immediately understood that the voltage on the node D is equal to the voltage present on the node A minus the three voltage drops on the selection switches 20, 21 and 22 that form the column selector 13, which are in turn proportional to the series resistances RON of the transistors that form the selection switches (when on), as well as to the current flowing therein.
Consequently, the voltage on the node D is affected by imprecisions due not only to the variations in the technological process used to implement the transistors that form the selection switches 20, 21 and 22 and on the variations of the current drawn by the memory cell 16, but also, and above all, to the temperature; moreover, the higher the number of selection switches that form the column selector 13, the less precise and controllable the voltage of the node D, both during programming and reading.
Furthermore, in the column decoding architecture shown in FIG. 4, the noise present on the node A, on the node B or on the node C and mainly consisting of fluctuations of the electrical potentials of these nodes is transmitted as such to the node D, with evident disturbance on the operation that is being carried out, whether reading or programming.
The aforesaid two factors of disturbance and imprecision on the biasing voltages of the array access device terminals of the memory cells, as previously mentioned, adversely affect the precision of the levels programmed in the memory cells, the corresponding programming time and the safe detection of the cell content in read operation: in other terms they affect yield, performance and reliability of the device.
In addition, when the aim is to reduce the biasing voltage of the array access device terminal of the addressed memory cell 16, for example to bring it as low as few hundred millivolts, as required by some non volatile memory technology, this problem becomes even more accentuated and may even jeopardize the robustness, if not indeed the feasibility, of nonvolatile memory devices having the aforesaid characteristics.
According to principals of the present invention a nonvolatile memory device is provided which can simultaneously different operations, for example reading and programming, on different groups of memory cells belonging to the same word line.